European Patent Application No. 05 028 281 A2 teaches a silicon capacitor which comprises an n-doped silicon substrate whose surface is structured in a characteristic fashion by an electrochemical etching in an acidic electrolyte containing fluoride in which the substrate is connected as an anode. In the electrochemical etching, more or less regularly arranged hole structures form at the surface of the substrate. The hole structures have an aspect ratio of up to around 1:1000. The surface of the hole structures is provided with a dielectric layer and a conductive layer. The conductive layer, dielectric layer and silicon substrate form a capacitor in which specific capacities of up to 100 .mu.V/mm.sup.3 are achieved due to the surface expansion that is effected by the hole structures. To increase the conductivity of the substrate, it is suggested to provide an n.sup.+ -doped region at the surface of the hole structures.
Silicon capacitors are typically produced in silicon disks. A bending of the silicon disk is established, which is brought into connection with mechanical strains by the n.sup.+ -doped zone at the surface of the hole structures, which are up to 300 .mu.m thick. This bending of the silicon disk leads to problems in further procedural steps such as lithography, disk thinning and isolation which are necessary for the installation of the silicon capacitor in a housing.
German Patent No. 44 28 195 C1 teaches a method for producing a silicon capacitor of this type. In order to compensate mechanical strains on the silicon substrate which are effected by the doping of the doped zone, the doped region is additionally doped with geranium. The additional doping with geranium leads to an increase in the complexity of processing
Therefore, there is need for a method for the production of a silicon capacitor which is simpler than the known method.
The above need is met by the inventive method wherein a plurality of hole structures are generated in a main surface of a silicon substrate. The hole structures comprise a round or polygonal cross-section and sidewalls that are essentially perpendicular to the main surface.
Along the surface of the hole structures, a conductive region is created which is provided with electrically active dopant. The conductive region forms a capacitor electrode in the finished silicon capacitor. It is preferably doped with phosphorous or boron.
A dielectric layer and a conductive layer are deposited on the surface of the conductive zone so as not to fill the hole structures. On the surface of the conductive layer, an auxiliary layer with essentially conformal edge coverage is formed, which layer is subjected to a compressive mechanical stress. Lastly, the hole structures are filled.
Due to the conductive zone which is provided with dopant and which extends along the surface of the hole structures, there results a concave bending of the silicon substrate if the dopant has a smaller covalent bond radius than silicon. This is true of phosphorous and boron. The use of the auxiliary layer, which is under a compressive mechanical stress and which is inserted in the hole structures with conformal edge coverage, effects a bending of the silicon substrate in the direction of a convex shape. This compensates the concave bending of the substrate that is effected by the conductive zone. Problems in the production of the silicon capacitor are thereby avoided. The concave bending of the silicon substrate has the disadvantage that, in conventional production devices, the substrates are held on carriers by low air pressure (what is known as vacuum chucks). A concave bending of the substrate leads to an inability to suck in the substrate, so that an automated production is not possible. On the other hand, slightly convexly shaped substrates can be sucked in on these carriers, since the substrate margin is inclined for sealing against atmospheric pressure.
A layer of thermal SiO.sub.2 is particularly suitable as an auxiliary layer that is under compressive mechanical stress. The incorporation of oxygen in the formation of SiO.sub.2 by the thermal oxidation of silicon leads to a compressive mechanical stress on the silicon base in the layer of thermal SiO.sub.2. Alternatively, a layer of undoped polysilicon can be used. In the growing of a polysilicon layer, in the bottom part of the layer there results a growth of many small crystallites which compete for further growth in the course of the layer deposition. The polysilicon layer is thus under a compressive mechanical stress.
If, subsequent to the formation of the hole structures, the conductive zone, the dielectric layer and the conductive layer, the silicon substrate comprises such a bend that there is a height difference of up to 500 .mu.m between the middle of the silicon substrate and the edge, then this concave bend can be compensated by an auxiliary layer of thermal oxide in a thickness of 30 to 250 nm. The thermal oxide auxiliary layer is under a compressive stress of approximately 10.sup.4 N/cm.sup.2. Given the utilization of an auxiliary layer of polysilicon, a layer thickness between 50 nm and 100 nm is required.
It is conceivable to compensate mechanical stresses in a silicon substrate which are conditioned by layers that contract more strongly than silicon by depositing a correspondingly thick silicon nitride layer on the back side of the silicon substrate. However, it has been demonstrated in the production of a silicon capacitor that such silicon nitride layers with manageable thicknesses of approximately 1 .mu.m cannot compensate the concave bend of the silicon substrate. Estimations have shown that the thickness of the silicon nitride layer on the back of the silicon substrate would have to be between 20 and 50 .mu.m thick. Such layer thicknesses are not feasible in terms of processing technology, however.
The hole structures are preferably formed by electrochemical etching in an acidic electrolyte containing fluoride, whereby the main surface is in contact with the electrolyte and a voltage is applied between the electrolyte and the silicon substrate such that the silicon substrate is connected as an anode. A back side of the silicon substrate, which is opposite the main surface, is illuminated during the electrochemical etching. Hole structures can thus be formed with diameters in the range from 0.5 .mu.m to 10 .mu.m and with depths in the range from 50 .mu.m to 500 .mu.m, said hole structures comprising an aspect ratio in the range from 30 to 300. The quotient of depth and diameter is defined as the aspect ratio. The higher the aspect ratio, the more aggravating the concave bend of the silicon substrate becomes, which is due to the conductive region which extends along the surface of the hole structures.
Alternatively, the hole structures can be formed by masked or unmasked anisotropic etching.
The dielectric layer is preferably formed as a multiple layer with a layer sequence of SiO.sub.2, Si.sub.3 N.sub.4 and SiO.sub.2. Such layers, which are often referred to as ONO layers, can be formed with very low defect densities. This is an essential precondition for the production of the silicon capacitor, which comprises a large surface due to the surface expansion by the hole structures.
For the production of contacts to the conductive layer and/or to the conductive zone, which contacts act as capacitor electrodes in the finished silicon capacitor, the surface of the conductive layer is preferably exposed in the region of the main surface. The auxiliary layer remains on the surface of the hole structures. Beyond this, for the contacting of the conductive zone, the surface of the conductive zone is exposed in the region of the main surface. Here, as well, the auxiliary layer remains in the region of the hole structures.